When generating power for driving a high-output motor by means of a power supply processing unit such as an inverter unit, it is necessary to provide a large-capacity power supply processing unit. However, such a large-capacity power supply processing unit has the following problems: 1) increased housing size 2) since the unit is often a custom-designed product, development cost is higher than when using a general-purpose power supply processing unit, and 3) increased maintenance cost.
In view of the above problems, it has been proposed, as shown in FIG. 1, to construct the windings of a high-output motor 1 from a plurality of electrically independent three-phase windings and connect a plurality of general-purpose power supply processing units 2 (2A, 2B, 2C, and 2D) to the respective three-phase windings to drive high-output motor 1. Since this configuration not only reduces the volume of each individual power supply processing unit, but also permits the use of general-purpose power supply processing units, development and maintenance costs can be reduced. However, the configuration of FIG. 1, has the disadvantage that the number of motors that can be connected to control processing unit 3 is limited. This is due a limit of the number of power supply processing units 2 that can be connected to control processing unit (CNC) 3.
FIG. 2 shows a motor control apparatus as proposed in Japanese Unexamined Patent Publication No. 2005-86918 to overcome the above disadvantage. In this apparatus, one signal relay processing unit (PDM) 4 is provided between control processing unit 3 and the plurality of power supply processing units 2 (2A, 2B, 2C, and 2D), and a motor drive command from control processing unit 3 is supplied to the plurality of power supply processing units 2 in a parallel fashion via signal relay processing unit 4. With this configuration, since signal relay processing unit (PDM) 4 can be handled as though it were one power supply processing unit, it is possible to connect a plurality of signal relay processing units 4 to control processing unit 3 and drive a large number of motors under the control of control processing unit 3. This solves the problem associated with the apparatus of FIG. 1, i.e., a limited number of motors that can be connected to it.
FIG. 3 is a diagram showing a signal control system in a motor control apparatus of the type shown in FIG. 1 in which motor control processing unit 3 is directly connected to power supply processing units 2. As shown, control processing unit 3 includes a receiving part 3a, a transmitting part 3b, and a preparation request flag 3c, and each power supply processing unit 2 includes a receiving part 2a, a transmitting part 2b, and a preparation complete flag 2c. When power supply processing unit 2 starts preparation for driving the motor, control processing unit 3 enables the preparation request flag. When the preparation for supplying power to the motor is completed, power supply processing unit 2 enables preparation complete flag 2c. The enabled or disabled state of preparation request flag 3c is transmitted via its transmitting part 3c to receiving part 2a of power supply processing unit 2. The enabled or disabled state of preparation complete flag 2c in supply processing unit 2 is transmitted via its transmitting part 2c to receiving part 3a of control processing unit 3.
FIGS. 4 and 5 are time charts illustrating the operation of the apparatus shown in FIG. 3. As shown in FIG. 4, control processing unit 3 at time T1 changes the state of preparation request flag 3c from disabled to enabled and transmits the preparation request flag enabled state to power supply processing unit 2, whereupon power supply processing unit 2 starts preparation for supplying power to the motor, and transmits the preparation complete flag enabled state to control processing unit 3 upon completion of the preparation (time T2). When control processing unit 3 receives the preparation complete flag enabled state from power supply processing unit 2 within a predefined time interval (T1 to T3), for example, within several seconds, control processing unit 3 outputs a motor drive command by determining that power supply processing unit 2 has completed the preparation for driving the motor. In order to effect the supply of power from power supply processing unit 2 to the motor, not only the condition that the motor drive command is received, but also other conditions, including the condition that an emergency stop signal (alarm) for stopping power supply processing unit 2 is disabled, must be satisfied.
On the other hand, if power supply processing unit 2 fails, in order to complete the preparation for supplying power to the motor in response to the preparation request flag enabled state transmitted from control processing unit 3, preparation complete flag 2c in power supply processing unit 2 continues to be held in the disabled state, as shown in FIG. 5. As a result, control processing unit 3 cannot receive the preparation complete flag enabled state within the predefined time interval, and therefore, at time T3 control processing unit 3 transmits the preparation request flag disabled state to power supply processing unit 2, causing power supply processing unit 2 to stop the preparation for driving the motor, and subsequently carries out alarm processing.
However, when the flag control shown in FIGS. 3 to 5 is applied to the motor control apparatus of the type shown in FIG. 2, the following problem occurs.
FIG. 6 is a block diagram showing the configuration when the flag control described above with reference to FIGS. 3 to 5 is applied to the motor control apparatus of the type shown in FIG. 2. As shown, signal relay processing unit 4 includes: a preparation request flag 4c which is enabled or disabled depending on the state of preparation request flag 3c received from control processing unit 3; a preparation complete flag register 4f which stores preparation complete flags 2c (2A to 2D) received from respective power supply processing units 2A to 2D; and a preparation complete flag 4d which is enabled or disabled according to the contents of preparation complete flag register 4f, that is, according to whether all the preparation complete flags from the respective power supply processing units 2A to 2D are enabled or not. Preparation complete flag register 4f is, for example, a four-bit register when four power supply processing units 2A to 2D are connected to signal relay processing unit 4, and each bit is set to a 1 or a 0 according to whether preparation complete flag 2c from a corresponding one of the power supply processing units is enabled or disabled.
Preparation complete flag 4d in signal relay processing unit 4 is enabled when the value of preparation complete flag register 4f is “1111”, i.e., when all the preparation complete flags received from the respective power supply processing units are in enabled state. On the other hand, when the value of preparation complete flag register 4f is not “1111”, i.e., when the preparation complete flag received from any one of the power supply processing unit is not in enabled state, preparation complete flag 4d is disabled. In signal relay processing unit 4, reference numeral 4a indicates a receiving part which receives the preparation request flag from control processing unit 3 and the preparation complete flags from the respective power supply processing units 2A to 2D, and 4b designates a transmitting part which transmits the state of preparation request flag 4c to power supply processing units 2A to 2D and the state of preparation complete flag 4d to control processing unit 3.
The operation of the apparatus shown in FIG. 6 and the problem associated with it will be described with reference to the time charts of FIGS. 7 and 8. As shown in FIG. 7, when preparation request flag 3c in control processing unit 3 changes from disabled to enabled at time T1, the preparation request flag enabled state is transmitted to signal relay processing unit 4, and preparation request flag 4c changes from disabled to enabled. This change of state is transmitted to the respective power supply processing units 2A to 2D in a parallel fashion, causing the power supply processing units to start preparation for driving the motor. Power supply processing units 2A, 2B, and 2C that have completed the preparation for supplying power to the motor change their preparation complete flags 2c (2A), 2c (2B), and 2c (2C) from disabled to enabled upon completion of the preparation (T4 and T5).
On the other hand, power supply processing unit 2D has failed to complete the power supply preparation due to some kind of trouble, and therefore, its preparation complete flag 2c (2D) continues to be held in the disabled state. As a result, the value of preparation complete flag register 4f in signal relay processing unit 4 does not change to “1111”, and preparation complete flag 4d cannot change to the enabled state. Since control processing unit 3 is not able to receive the enable signal of preparation complete flag 4d from signal relay processing unit 4 within the predefined time after changing the preparation request flag from disabled to enabled, preparation request flag 3c is automatically changed from enabled to disabled at time T3. Since this change of state is transmitted to the respective power supply processing units 2A to 2D in a parallel fashion via preparation request flag 4c in signal relay processing unit 4, the preparation complete flags in the respective power supply processing units 2A to 2D are forcefully disabled at time T6. This information is transmitted to signal relay processing unit 4 at time T7, updating the contents of the preparation complete flag register to “0000”. When preparation request flag 3c in control processing unit 3 is changed from disabled to enabled, preparation complete flag register 4f in signal relay processing unit 4 may be reset as shown at time T8.
As described above, in the apparatus shown in FIG. 6, when control processing unit 3 does not receive the enabled state of preparation complete flag 4d from signal relay processing unit 4 within the predefined time after enabling preparation request flag 3c, preparation request flag 3c is automatically changed from enabled to disabled, and the preparation complete flags in the respective power supply processing units 2A to 2D are forcefully disabled, as a result of which the contents of preparation complete flag register 4f in signal relay processing unit 4 are updated to “0000”. In this case, control processing unit 3 cannot identify the failed power supply processing unit from the value of preparation complete flag register 4f. 
FIG. 8 is a time chart showing the flag states in the respective processing units when the states of preparation complete flags 2c (2A to 2D) in the respective power supply processing units connected to the signal relay processing unit 4 are all enabled but a certain power supply processing unit, for example, power supply processing unit 2D, fails when power is being normally supplied to the motor. In the case where control processing unit 3 has transmitted the enabled state of preparation request flag 3c, and in response, power supply processing units 2A to 2D have started operating normally and preparation complete flags 2c (2A) to 2c (2D) are transmitting enabled states. In this case, if power supply processing unit 2D fails at time T10, causing its preparation complete flag 2c (2D) to change from enabled to disabled, information notifying this change of state is received by signal relay processing unit 4 which, at time T11, updates the contents of the preparation complete flag register from “1111” to “0111” and changes the preparation complete flag 4d from enabled to disabled.
This enabled to disabled state change of preparation complete flag 4d is transmitted to control processing unit 3, whereupon the preparation request flag 3c in control processing unit 3 changes from enabled to disabled. Then, at time T12, preparation request flag 4c in signal relay processing unit 4 is caused to change from enabled to disabled. This change of state is transmitted to power supply processing units 2A to 2D in a parallel fashion (time T13), and as a result, all of preparation complete flags 2c (2A) to 2c (2D) are disabled, in response to which preparation complete flag register 4f in signal relay processing unit 4 is cleared to “0000” at time T14. As a result, as in the case of FIG. 7, control processing unit 3 cannot identify the failed power supply processing unit from the value of preparation complete flag register 4f. 